Make various preparations for upcoming features

A lot of this is random WIP from a while back, at least a month ago, and
is being committed now to get it out of the way so that other patches
can be brought in and integrated against it without causing headaches.

Also rolled into this commit is a way to distinguish plugin_unload from
exiting the game. This is required for another soon-to-be-integrated
feature to avoid crashing on exit, and could in theory also be used to
speed up unloading on exit in future. While we're at it, this also
avoids the need to linearly scan through the plugin list to do the
old branch unloading fix, because we can.

Rough summary of the other smaller stuff I can remember doing:
- Rework bitbuf a bit
- Add some cryptographic nonsense in ac.c (not final at all)
- Introduce the first couple of "chunklets" libraries as a sort-of
  subproject of this one
- Tidy up random small bits and bobs
- Add source for a small keypair generation tool
- Rework democustom to be very marginally more useful

1 files changed, 45 insertions, 0 deletions

diff --git a/src/chunklets/cacheline.h b/src/chunklets/cacheline.h
new file mode 100644
index 0000000..cadd55d
--- /dev/null
+++ b/src/chunklets/cacheline.h
@@ -0,0 +1,45 @@
+/* This file is dedicated to the public domain. */
+
+#ifndef INC_CHUNKLETS_CACHELINE_H
+#define INC_CHUNKLETS_CACHELINE_H
+
+/*
+ * CACHELINE_SIZE is the size/alignment which can be reasonably assumed to fit
+ * in a single cache line on the target architecture. Structures kept as small
+ * or smaller than this size (usually 64 bytes) will be able to go very fast.
+ */
+#ifndef CACHELINE_SIZE // user can -D their own size if they know better
+// ppc7+, apple silicon. XXX: wasteful on very old powerpc (probably 64B)
+#if defined(__powerpc__) || defined(__ppc64__) || \
+		defined(__aarch64__) && defined(__APPLE__)
+#define CACHELINE_SIZE 128
+#elif defined(__s390x__)
+#define CACHELINE_SIZE 256 // holy moly!
+#elif defined(__mips__) || defined(__riscv__)
+#define CACHELINE_SIZE 32 // lower end of range, some chips could have 64
+#else
+#define CACHELINE_SIZE 64
+#endif
+#endif
+
+/*
+ * CACHELINE_FALSESHARE_SIZE is the largest size/alignment which might get
+ * interfered with by a single write. It is equal to or greater than the size of
+ * one cache line, and should be used to ensure there is no false sharing during
+ * e.g. lock contention, or atomic fetch-increments on queue indices.
+ */
+#ifndef CACHELINE_FALSESHARE_SIZE
+// modern intel CPUs sometimes false-share *pairs* of cache lines
+#if defined(__i386__) || defined(__x86_64__) || defined(_M_X86) || \
+	defined(_M_IX86)
+#define CACHELINE_FALSESHARE_SIZE (CACHELINE_SIZE * 2)
+#elif CACHELINE_SIZE < 64
+#define CACHELINE_FALSESHARE_SIZE 64 // be paranoid on mips and riscv
+#else
+#define CACHELINE_FALSESHARE_SIZE CACHELINE_SIZE
+#endif
+#endif
+
+#endif
+
+// vi: sw=4 ts=4 noet tw=80 cc=80